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Silicon Labs /BGM240PB32VNA /MODEM_NS /SICTRL2

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Interpret as SICTRL2

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https://regviz.com/r/Silicon Labs/EFR32MG24A010F1536GM40/MODEM_S/SICTRL2#0x0

31282724232019161512118743000000000000000000000000000000000000000000 (SIRSTAGCMODE)SIRSTAGCMODE0 (SIRSTPRSMODE)SIRSTPRSMODE0 (SIRSTCCAMODE)SIRSTCCAMODE0SUPERCHIPTHRESH0 (DISSIFRAMEDET)DISSIFRAMEDET0 (AGCRSTUPONSI)AGCRSTUPONSI

Description

No Description

Fields

SIRSTAGCMODE

SI reset by AGC
SIRSTPRSMODE

SI reset by PRS PAEN
SIRSTCCAMODE

SI reset by CCA req
SUPERCHIPTHRESH

Superchip pass threshold
DISSIFRAMEDET

Disable SI when framedet
AGCRSTUPONSI

AGC reset on SI reset

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data